PLD/ASIC SOLUTIONS

Introducing the Industry’s Lowest Power, High-End FPGAs

Altera has introduced Stratix® III, its 65nm high-end FPGA family. Based on extensive customer feedback, the new series has been designed to bring not only the expected benefits of improved density, performance and cost, but also a significant reduction in power consumption and increased design productivity.

To allow the designer to select a device that closely matches the mix of resources needed, Stratix III offers various sub-families. The Base devices are suitable for general applications such as balanced logic, memory and multipliers. The Enhanced range is designed for memory- and DSP-rich applications, with the emphasis on providing memory and multipliers, rather than logic. These devices are aimed at wireless, medical imaging and military applications.

For high-bandwidth uses such as telecoms, broadcast, test equipment, computer and storage applications, the Stratix III GX series provides integrated Gigabit transceivers. Finally, for truly high-volume applications, the HardCopy® III range provides ASIC-like characteristics of low unit cost, higher performance and low power consumption.

Multiple techniques are employed to provide a dramatic reduction in both dynamic and static power consumption, along with the ability to run full designs 25% faster. These include a core operating voltage which is selectable between 1.1V and 0.9V; patented programmable power technology that enables every logic block to work at high speed or in a low-power mode, depending on design requirements; and proprietary PowerPlay optimisations within the Quartus II design software.

The Quartus II tool suite automatically analyses the design and identifies which blocks demand the highest performance, setting these to high-speed mode (the rest are set to low-power mode). The result is an average reduction in dynamic power of 33% to 55%, and an even greater cut in static power of 52% to 64% when compared with previous generation FPGAs.



In addition to advanced silicon features, the Quartus® II design software offers advanced place and route technology, physical synthesis, and the TimeQuest timing analyser to accelerate timing closure. The industry’s first and most comprehensive incremental compilation feature also reduces design cycles by shortening compile times.

Leading embedded and DSP system design tools, including SOPC Builder and DSP Builder, automate system design from front to back. These tools provide a wide array of IP cores (including the Nios® II embedded processor, memory, interface, control, and your own proprietary functions), which can be customised before automatic generation of hardware, software, and simulation models.

Device Overview

Stratix III Version	Device	ALMs	Equivalent LEs	Registers	M9K Blocks	M144K Blocks	Embedded Memory (Bits)	MLAB (Bits)	Maximum 18x18 Multipliers
Stratix III L	EP3SL50	19K	48K	38K	108	6	1.8M	0.6M	216
Stratix III L	EP3SL70	27K	68K	54K	144	6	2.1M	0.9M	288
Stratix III L	EP3SL110	43K	107K	86K	275	12	4.2M	1.4M	288
Stratix III L	EP3SL150	57K	142K	114K	340	16	5.2M	1.8M	384
Stratix III L	EP3SL200	80K	199K	160K	456	24	7.4M	2.6M	576
Stratix III L	EP3SE260	102K	254K	204K	828	40	14.7M	3.3M	704
Stratix III L	EP3SL340	135K	338K	270K	1,144	48	16.8M	4.3M	576
Stratix III E	EP3SE50	19K	48K	38K	336	12	4.6M	0.6M	384
Stratix III E	EP3SE80	32K	80K	64K	495	12	6.2M	1.0M	672
Stratix III E	EP3SE110	43K	107K	86K	544	16	7.0M	1.4M	896
Stratix III E	EP3SE260	102K	254K	204K	828	40	14.7M	3.3M	704

Features

• Full range of FPGAs based on 65nm technology
• 340,000 equivalent Logic Elements (LEs), 21Mbit memory
• 25% higher performance
• 50% lower power
• Up to 896 18 x 18 multipliers with 550MHz DSP performance
• Up to 24 high-performance I/O banks and very broad pin-out compatible density migration
• Best-in-class signal integrity
• Design security with non-volatile-based configuration stream encryption
• Seamless migration to structured ASIC with HardCopy III

Applications

• General-purpose
  • Balanced logic, memory and multipliers
• Memory- and DSP-rich applications
  • Wireless
  • Medical imaging
  • Military
• High interface bandwidth applications
  • Telecom
  • Broadcast
  • Test equipment
  • Computing and storage
• HardCopy III for high-volume applications

For further information, including the Stratix III Device Handbook, and to learn more about Designing Stratix III FPGAs with Quartus II (and to download the Quartus II Software), please click here.

Alternatively, call your local Arrow FAE who will be able to support you in all aspects of your FPGA implementation.