ENGINEERING FEATURE

Supporting FPGA Designs

In addition to offering a variety of FPGA technologies, Arrow can also provide support tools and engineering expertise that simplifies and speeds the development of FPGA-based applications. Here we look at some of those tools in the context of the latest FPGA developments from Altera, Lattice Semiconductor and Atmel.

High levels of programming flexibility have made FPGAs popular when it comes to design, development and prototyping of embedded applications. What’s more, thanks to a combination of factors such as ongoing cost reduction, improved performance and reduced power consumption, FPGAs are increasingly making it past the development phase and on into final production.

The growth in the use of FPGAs means that more and more engineers are now faced with the prospect of developing applications using these devices. The good news is that, whether it's software tools or reference designs, IP (Intellectual Property) cores or starter kits, there are a large number of support tools to help engineers get the most from their FPGA design - in the shortest possible time and at the lowest possible cost.

Altera Arria™ GX Transceiver-Based FPGAs

Launched in May 2007, the Altera Arria™ GX family provides an excellent example of both the latest low cost transceiver-based FPGA technologies and the types of support that are now available to the design engineer looking to work with these technologies.

Arria GX FPGAs are designed to address the rapidly growing need for low cost FPGAs with transceivers in the communications, computer, storage and industrial markets. The devices are optimised to support PCI Express (PCIe), Gigabit Ethernet (GbE) and Serial RapidIO™ (SRIO) standards up to 2.5Gbps - standards that are rapidly emerging as mainstream protocols in a wide variety of markets and applications.

The Arria GX family comprises five devices ranging in density from 21,580 to 90,220 Logic Elements (LEs), up to 4.5Mbits of embedded memory and up to 176 multipliers. The technology is built around TSMC’s established 90nm process. Features of the Arria GX family include Altera’s proven Stratix® II GX transceiver technology and flip-chip packages which provide a significant signal integrity advantage over wire-bond packages when combining transceivers with advanced memory interfaces.

The Altera Arria GX FPGAs provide up to 12 full duplex transceiver channels optimised to implement the PCIe, GbE and SRIO protocols. Implementing these protocols from a design perspective is significantly simplified by the availability of verified and configurable IP cores for each of the individual standards. These cores meet all requirements for compliance and interoperability. By combining such IP subsystem solutions with the Arria GX hardware, engineers can quickly develop a low cost, single chip solution that bridges multiple protocols (Figure 1).


Figure 1: A Typical Arria GX Bridging Application

In addition to the verified IP cores, Arria GX FPGAs offer a design environment that includes software tools, complete characterisation reports, reference designs, and protocol-specific development kits with support for PCIe x1 and x4, SRIO and Gigabit Ethernet. A key element of this support is the easy-to-use Quartus® II development software. This software provides a complete, multiplatform design environment that easily adapts to specific design needs. It is a comprehensive environment for System-On-a-Programmable-Chip (SOPC) design and includes solutions for all phases of FPGA design (Figure 2).


Figure 2: Quartus II Design Flow

Designed to enable the highest levels of productivity and the fastest path to design completion, Quartus II offers a number of productivity enhancing features including:

• TimeQuest Timing Analyzer
  • Complete GUI environment for creating constraints and timing reports
  • ASIC strength features including support for Synopsis Design Constraints format
• PowerPlay power analysis and optimisation technology
  • Provides automated power optimisation capabilities and helps effectively manage power from design concept through implementation
• Incremental compilation
  • Supports bottom-up design flow that allows design blocks to be created and optimised independently
• SOPC Builder: eliminates mundane and error-prone system integration tasks and allows systems to be built in minutes
• Extensive cross-probing support between tools
  • Helps identify and correct design issues
• Pin planner feature
  • Enables easy I/O pin assignment planning, assignment, and validation
• Advanced scripting capabilities

LatticeECP2M™ FPGA Technology

Lattice Semiconductor is another company offering IP cores that allow its FPGAs to meet the needs of applications based on the latest communication protocols. Earlier this year, for example, the company announced the expansion of its PCI Express IP core family with the addition of a new PCI Express x4 solution optimised for the LatticeECP2M™ low cost FPGA family.


Figure 3: LatticeECP2M FPGAs

Like its previous PCI Express x1 IP core for LatticeECP2M devices, the x4 version implements a single-chip PCI Express endpoint solution with integrated SERDES that is ideal for high-volume, low-cost and limited form factor applications. The LatticeECP2M core implements the transaction, data link and most of the physical layer in soft IP. The remainder of the physical layer – including clock tolerance compensation, 8b/10b encoding and link synchronisation – is completely embedded in the low cost LatticeECP2M Physical Coding Sublayer (PCS), which fully supports 2.5Gbps operation. As a result, with the LatticeECP2M core, customers benefit from a high performance and fully integrated PCI Express solution combined with low-cost PCS/SERDES: a compelling value for high-volume applications.

And once again the emphasis is not simply on the technology but also on the design support. As well as the IP core, Lattice’s PCI Express x4 solution includes an evaluation board, demonstration software and drivers. The LatticeECP2M evaluation board is available in the PCI Express mechanical form factor compatible with standard motherboards, while the demonstration software uses the evaluation boards to demonstrate PCI express endpoint operation. This includes configuration, memory/register access and simple tests. Demo drivers and API are also available for users who wish to extend the demo capabilities.


Figure 4: LatticeECP2M PCI Express x4 Evaluation Board

Lattice’s PCI Express IP cores are supported in the company’s ispLEVER® design tool suite. The ispLEVER software family provides a complete set of powerful tools for all design tasks, including project management, IP integration, design planning, place and route and in-system logic analysis.

Atmel AT40K and AT40KAL FPGAs

Atmel’s low cost AT40K and AT40KAL series FPGAs offer usable gates of between 5,000 and 50,000 and are designed for high density, compute-intensive DSP and other fast logic designs. The devices feature an innovative distributed RAM architecture that removes the traditional trade-off between memory and logic resources. Targeted at common co-processor applications, the Atmel FPGAs support system speeds of up to 100MHz, and can perform array multiplication at over 50MHz.

In addition to the standard FPGAs, Atmel’s AT40K/AT40KAL technology is also available as an embedded core. The first family of products based on this technology is the FPSLIC™ family. FPSLIC (Field Programmable System Level Integrated Circuits) devices combine between 5,000 and 50,000 gates with up to 36K of SRAM and a 25MHz AVR MCU.

The AT40K and AT40KAL devices are FPGAs with the ability to implement cache logic design, where part of the FPGA can be reprogrammed without loss of register data, while the remainder of the FPGA continues to operate without disruption. This is ideal for building adaptive filters, variable coefficient multipliers and other designs where the datapath can change to increase system performance.

A key element of the support that Atmel provides for its AT40K/AT40KAL technologies is its FPGA Integrated Development System (IDS). The IDS lets designers create fast, predictable designs with AT40K/AT40KAL FPGAs with HDL Planner for VHDL and Verilog Entry. IDS is a ‘place and route’ tool that can be used in conjunction with other popular synthesis tool environments. IDS is available as a standalone tool in addition to being integrated into System Designer Software which is a complete package for FPSLIC/FPGA design.


Figure 5: Atmel IDS GUI

Atmel has also developed a wire wrap prototyping system for the AT40K/AT40KAL FPGAs. Known as the ATDH40M, this system allows designers to quickly and economically evaluate the Atmel FPGAs. The ATDH40M board allows programming of the devices from any x86 PC via a parallel port and a 10-pin header cable. The motherboard interfaces with various daughter boards in order to program different package footprints.

Altera® Cyclone III

The final technology we are going to look at in this article is Altera’s Cyclone® III, which offers an unprecedented combination of low power, high functionality and low price. Cyclone III FPGAs are manufactured using Taiwan Semiconductor Manufacturing Company's (TSMC's) 65nm Low Power (LP) process technology to deliver low power consumption at a price that rivals that of ASICs.

The Cyclone III family comprises eight devices ranging from 5,000 to 120,000 LEs and up to 535 user I/O pins. Cyclone III devices offer up to 4Mbit of embedded memory, 288 embedded 18-bit x 18-bit multipliers, dedicated external memory interface circuitry, Phase-Locked Loops (PLLs), and high-speed differential I/O capabilities. A broad range of devices and package options support a wide variety of cost sensitive high volume applications.

To help users evaluate and prototype applications based on Cyclone III FPGAs, Altera has created the Cyclone III FPGA Starter Development Kit. An ideal introduction for users who have no previous experience of designing with FPGAs, the Starter Kit also provides resources that will suit the more experienced FPGA developer.


Figure 6: Cyclone III Starter Kit

The Cyclone III FPGA Starter Development Kit features the Cyclone III Starter Board, an FPGA Starter Kit CD-ROM and download instructions for the latest development software (including the Quartus II tools mentioned previously).

The Starter Board features:

• Cyclone III EP3C25F324 FPGA
• Embedded USB-Blaster™ circuitry (includes an Altera EPM3128A CPLD) allowing download of FPGA configuration files via the user’s USB port
• Power and analogue devices from Linear Technology
  • Switching power supply LTM4603EV-1
  • Switching and step-down regulators LTC3413, LT1959
• Memory
  • 256Mbit DDR SDRAM
  • 1Mbyte synchronous SRAM
  • 16Mbytes Intel P30/P33 flash
• Clocking
  • 50MHz on-board oscillator
• Switches and indicators
  • Six push buttons (four user controlled)
  • Seven LEDs (four user controlled)
• Connectors
  • High Speed Mezzanine Connector (HSMC)
  • Supporting 13 user controlled LVDS I/O channels and associated control signals
  • USB type B
• Cables and power
  • USB cable
  • External power supply

On the Cyclone III FPGA Starter Kit CD-ROM users will find example designs and complete documentation, including a user guide, reference manual, board schematic and layout, BOM and product and partner information.

Additional Support

Of course Arrow’s support for FPGA designs goes beyond the ability to provide the FPGAs and supply tools such as those highlighted above. The company also offers extensive technical support, including trained engineers who can do everything from advising on product selection to helping with device programming and configuration and physical circuit design and development. What’s more, we can also provide all of the semiconductor, passive component, power supply, interconnect and electromechanical devices needed to take an FPGA design from initial conception to finished product.

To find out more about FPGA and other programmable logic technologies and support from Arrow, please click here