POWER AND LINEAR IC SOLUTIONS

Simplified IF Digitisation for Base Station Receivers

Employing System in Package (SiP) technology and the latest components, LTC has developed a simplified IF (Intermediate Frequency) receiver that solves some of the key challenges of design an IF receiver.



Modern receivers digitally demodulate the in-phase and quadrature information using powerful FPGAs and DSPs instead of analogue techniques. The receivers recover the carrier frequency and symbol clock serially from the ADC output. High speed ADCs are necessary to support high sensitivity communications receivers; as more processing takes place in the digital domain, the IF at which a signal is digitised and the dynamic range increase.

Software defined radios need high linearity and a good dynamic range; several new ADCs from Linear Technology have sufficient levels of each, however, utilising their available performance requires some expertise in RF and mixed signal disciplines. To minimise the software-radio design challenges, Linear Technology has used SiP technology for its LTM9001 16-bit, 130Msps IF-sampling receiver subsystem.

The LTM9001 includes a high-speed 16-bit A/D converter, matching network, anti-aliasing filter and a low noise, differential amplifier with fixed gain. It can digitise a wide dynamic range of signals with an IF range up to 300MHz. The amplifier accepts an AC- or DC-coupled input drive. A designer can specify a low-pass or band-pass filter network with various bandwidths.

The LTM9001 is perfect for IF receivers in demanding communications applications; its AC performance includes 72dBFS noise floor and 82dB Spurious Free Dynamic Range (SFDR) at 162.5MHz (LTM9001-AA). The outputs can be differential LVDS or single-ended CMOS in one of two formats: a single bus running at the full data rate or demultiplexed buses running at half data rate. A separate output power supply allows the CMOS output swing to range from 0.5V to 3.3V.

The drive for the differential ENC+ and ENC– inputs may be a sine wave, PECL, LVDS, TTL or CMOS inputs. An optional clock duty-cycle stabiliser allows high performance at full speed with a wide range of clock duty cycles.

Features

• Integrated 16-bit, high-speed ADC, passive filter and fixed gain differential amplifier
• <300MHz IF range
• Low-pass and band-pass filter versions
• Low noise, low distortion amplifiers
• Fixed gain: 8dB, 14dB, 20dB or 26dB
• Noise figure as little as 5.9dB
• 50Ω, 200Ω or 400Ω input impedance
• 72dB SNR, 82dB SFDR (LTM9001-AA)
• Integrated bypass capacitance, no external components required
• Optional internal dither
• Optional data output randomiser
• LVDS or CMOS outputs
• 3.3V single supply
• Power dissipation: 1.65W
• Clock duty cycle stabiliser
• LGA package, 11.25mm × 11.25mm × 2.32mm

Applications

• Telecommunications
• High sensitivity receivers
• Cellular base stations
• Spectrum analysers

For further information, including the Linear Technology LTM9001 Datasheet, please click here