POWER AND LINEAR IC SOLUTIONS

Reducing Digital Feedback in High Speed ADC Systems

Eliminating digital feedback in an analogue-to-digital conversion chain can be a challenge, even when board designers take care to isolate the analogue signal chain and encode clock from the digital outputs. Linear Technology Corporation offers ultra-low-power ADCs (Analogue/Digital Converters) with proprietary features to reduce this problem.

Causes of digital feedback include capacitive coupling, ground currents or even waveguide action. Small amounts of feedback can cause significant problems. When an ADC with no offset receives a very weak signal, it effectively acts as a high gain amplifier, i.e. driven in concert the outputs deliver significant power at the same frequency as the input signal.



In the worst case, at midscale, all of the ADC outputs may simultaneously switch from ones to zeros (or vice versa), generating a large ground current. Small signals crossing this midscale point produce a disproportionate output power in the summation of all these digital outputs.

The LTC2262 family includes 14-bit and 12-bit ADCs with sampling rates from 25MSPS to 150MSPS. They can limit digital feedback via an Alternate Bit Polarity (ABP) mode that inverts all of the odd bits before the output buffers. This produces an equal number of ones and zeroes when operating around midscale. The resulting ground-plane currents effectively cancel, reducing the energy fed back for small input signals.



In addition to the ABP mode, an optional data output randomiser is available that further reduces interference from the digital outputs.

The LTC2262 family requires as little as one-third the power of comparable ADCs, just 160mW for 14-bit 150MSPS operation and 30mW at 25MSPS. A nap or sleep mode reduces power even further, to 0.5mW.

In addition, the LTC2262 family is programmable via the SPI-compatible interface. Users can select between CMOS, DDR CMOS, DDR LVDS outputs, choose from seven LVDS output current settings, or enable optional LVDS output termination to help absorb any reflections caused by imperfect termination at the receiver. The device can also produce test patterns to allow a user to verify the connection between the ADC and processor.

Features

• 12-bit and 14-bit ADCs
• Digital feedback reduction
  • Alternate bit polarity mode
  • Randomisation
• 73.4dB SNR, 85dB SFDR (14-bit)
• Sample rate: 25MSPS to 150MSPS
• Low power: 30mW to 160mW
• Single 1.8V supply
• CMOS, DDR CMOS or DDR LVDS outputs
• Selectable input ranges: 1V to 2V peak to peak
• 800MHz full-power bandwidth sample and hold
• Optional clock duty cycle stabiliser
• Shutdown and nap modes
• SPI port for configuration
• 6mm × 6mm 40-pin QFN package

Applications

• Communications
• Cellular base stations
• Software defined radio
• Portable medical imaging
• Multi-channel data acquisition
• Non-destructive testing

For further information, to register your interest in a Free Demo Board*, or to obtain a copy of the latest Altera/LTC Development Tools Brochure, please click here

* Free demo boards are limited to current or potential Arrow customers with valid opportunities and are at the discretion of local Arrow representatives.